Static consistency checking for Verilog wire interconnects
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Publication:1929355
DOI10.1007/s10990-011-9072-1zbMath1256.68027OpenAlexW2200498803MaRDI QIDQ1929355
Publication date: 8 January 2013
Published in: Higher-Order and Symbolic Computation (Search for Journal in Brave)
Full work available at URL: https://doi.org/10.1007/s10990-011-9072-1
dependent typesVerilog elaborationdead code eliminationstatic array bounds checkingVerilog wire width consistency
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