TeLEx: learning signal temporal logic from positive examples using tightness metric
DOI10.1007/S10703-019-00332-1zbMATH Open1425.68349OpenAlexW2912432686WikidataQ128544015 ScholiaQ128544015MaRDI QIDQ2008282FDOQ2008282
Ashish Tiwari, Natarajan Shankar, Susmit Jha, Tuhin Sahai, Sanjit A. Seshia
Publication date: 25 November 2019
Published in: Formal Methods in System Design (Search for Journal in Brave)
Full work available at URL: https://escholarship.org/uc/item/5sj2g464
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Cites Work
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- Synthesis of Joint Control and Active Sensing Strategies Under Temporal Logic Constraints
- Robust Satisfaction of Temporal Logic over Real-Valued Signals
- S-TaLiRo: A Tool for Temporal Logic Falsification for Hybrid Systems
- Checking Temporal Properties of Discrete, Timed and Continuous Behaviors
- Learning regular languages from simple positive examples
- A theory of formal synthesis via inductive learning
- On Optimal Control of Stochastic Linear Hybrid Systems
- Quantitative monitoring of STL with edit distance
- Robust control for signal temporal logic specifications using discrete average space robustness
- Temporal logic inference for classification and prediction from data
- A Decision Tree Approach to Data Classification using Signal Temporal Logic
- Quantifying conformance using the Skorokhod metric
Cited In (5)
- Survey on mining signal temporal logic specifications
- Learning specifications for labelled patterns
- An automated system repair framework with signal temporal logic
- A program logic to verify signal temporal logic specifications of hybrid systems
- Adaptive testing for specification coverage and refinement in CPS models
Uses Software
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