Approximate evaluation of the efficiency of synchronous and self-timed methodologies in problems of designing failure-tolerant computing and control systems

DOI10.1134/S0005117922020084zbMATH Open1489.93079OpenAlexW4223506456MaRDI QIDQ2139484FDOQ2139484

Authors: I. A. Sokolov, Yu. A. Stepchenkov, Yu. V. Rogdestvenski, Yu. G. Diachenko 

Publication date: 17 May 2022

Published in: Automation and Remote Control (Search for Journal in Brave)

Full work available at URL: https://doi.org/10.1134/s0005117922020084

Recommendations

• scientific article; zbMATH DE number 48203
• Rigorously modeling self-stabilizing fault-tolerant circuits: an ultra-robust clocking scheme for systems-on-chip
• Formal Techniques for Networked and Distributed Systems - FORTE 2005
• Economic efficiency of fault tolerance
• scientific article; zbMATH DE number 1696499

zbMATH Keywords

hardwarefailureindicationsynchronous circuitfailure toleranceC-elementdual-rail signalself-timed circuit

Mathematics Subject Classification ID

Fault detection; testing in circuits and networks (94C12) Digital control/observation systems (93C62) Control/observation systems involving computers (process control, etc.) (93C83)

Cites Work

• Title not available (Why is that?)
• Fault-tolerant design

This page was built for publication: Approximate evaluation of the efficiency of synchronous and self-timed methodologies in problems of designing failure-tolerant computing and control systems

Report a bug (only for logged in users!)Click here to report a bug for this page (MaRDI item Q2139484)