Garbled circuits with sublinear evaluator

DOI10.1007/978-3-031-06944-4_2MaRDI QIDQ2169991zbMATH OpenOpenAlexFDO

Authors Abida Haque, Vladimir Kolesnikov, Steve Lu, Rafail Ostrovsky, Akash Shah, David G. Heath

Publication date 30 August 2022

Full work available at URL https://doi.org/10.1007/978-3-031-06944-4_2

zbMATH Keywords

GC WIth sublinear evaluatorstacked garbled circuit

Mathematics Subject Classification ID

Data encryption (aspects in computer science) (68P25) Cryptography (94A60)

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Cites work

• \textsf{LogStack}: stacked garbling with \(O(b \log b)\) computation
• A Practical Universal Circuit Construction and Secure Evaluation of Private Functions
• A proof of security of Yao's protocol for two-party computation
• Efficient Fully Homomorphic Encryption from (Standard) LWE
• Flexor: Flexible garbling for XOR gates that beats free-XOR
• Free IF: how to omit inactive branches and implement \(\mathcal{S}\)-universal garbled circuit (almost) for free
• Fully homomorphic encryption using ideal lattices
• Homomorphic encryption from learning with errors: conceptually-simpler, asymptotically-faster, attribute-based
• How to garble RAM programs?
• How to run Turing machines on encrypted data
• scientific article; zbMATH DE number 1261806 (Why is no real title available?)
• Improved Garbled Circuit: Free XOR Gates and Applications
• Multiparty Computation from Somewhat Homomorphic Encryption
• On the security of the ``Free-XOR technique
• Overlaying conditional circuit clauses for secure computation
• Privacy-free garbled circuits with applications to efficient zero-knowledge
• Private information retrieval
• Private information retrieval with sublinear online time
• Pushing the limits of Valiant's universal circuits: simpler, tighter and more compact
• Secure two-party computation is practical
• Stacked garbling for disjunctive zero-knowledge proofs
• Stacked garbling. Garbled circuit proportional to longest execution path
• Three halves make a whole? Beating the half-gates lower bound for garbled circuits
• Turbospeedz: double your online SPDZ! Improving SPDZ using function dependent preprocessing
• Two halves make a whole: reducing data transfer in garbled circuits using half gates
• Universal circuits (Preliminary Report)

Cited in

(3)

• Sok: vector OLE-based zero-knowledge protocols
• Garbling, stacked and staggered. Faster \(k\)-out-of-\(n\) garbled function evaluation
• Garbled circuit lookup tables with logarithmic number of ciphertexts

Describes a project that uses

Uses Software

• FleXOR

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