A parameterized multilevel pattern matching architecture on FPGAs for network intrusion detection and prevention

DOI10.1007/S11432-009-0024-XzbMATH Open1192.68609OpenAlexW2080624378MaRDI QIDQ2267141FDOQ2267141

Authors: Tian Song, Dongsheng Wang, Zhizhong Tang 

Publication date: 26 February 2010

Published in: Science in China. Series F (Search for Journal in Brave)

Full work available at URL: https://doi.org/10.1007/s11432-009-0024-x

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zbMATH Keywords

pattern matchingnetwork securitynetwork intrusion detectionnetwork intrusion prevention

Mathematics Subject Classification ID

Pattern recognition, speech recognition (68T10)

Cites Work

• Efficient string matching
• A fast string searching algorithm
• Fast Pattern Matching in Strings
• A parameterized multilevel pattern matching architecture on FPGAs for network intrusion detection and prevention

Cited In (6)

• Title not available (Why is that?)
• Title not available (Why is that?)
• An efficient pre-filtering mechanism for parallel intrusion detection based on many-core GPU
• A parameterized multilevel pattern matching architecture on FPGAs for network intrusion detection and prevention
• Fast multi-pattern matching algorithm for intrusion detection
• A high speed reconfigurable firewall based on parameterizable FPGA-based content addressable memories

Uses Software

• Snort

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