A parameterized multilevel pattern matching architecture on FPGAs for network intrusion detection and prevention
From MaRDI portal
Publication:2267141
Recommendations
Cites work
Cited in
(6)- scientific article; zbMATH DE number 1941098 (Why is no real title available?)
- scientific article; zbMATH DE number 1941093 (Why is no real title available?)
- An efficient pre-filtering mechanism for parallel intrusion detection based on many-core GPU
- A parameterized multilevel pattern matching architecture on FPGAs for network intrusion detection and prevention
- Fast multi-pattern matching algorithm for intrusion detection
- A high speed reconfigurable firewall based on parameterizable FPGA-based content addressable memories
This page was built for publication: A parameterized multilevel pattern matching architecture on FPGAs for network intrusion detection and prevention
Report a bug (only for logged in users!)Click here to report a bug for this page (MaRDI item Q2267141)