A parameterized multilevel pattern matching architecture on FPGAs for network intrusion detection and prevention

DOI10.1007/S11432-009-0024-XMaRDI QIDQ2267141zbMATH OpenOpenAlexFDO

Authors Tian Song, Dongsheng Wang, Zhizhong Tang

Publication date 26 February 2010

Published in Science in China. Series F (Search for Journal in Brave)

Full work available at URL https://doi.org/10.1007/s11432-009-0024-x

zbMATH Keywords

network intrusion detectionnetwork intrusion preventionnetwork securitypattern matching

Mathematics Subject Classification ID

Pattern recognition, speech recognition (68T10)

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Cites work

• A fast string searching algorithm
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• Efficient string matching
• Fast Pattern Matching in Strings

Cited in

(6)

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• Fast multi-pattern matching algorithm for intrusion detection
• An efficient pre-filtering mechanism for parallel intrusion detection based on many-core GPU
• Granidt: Towards gigabit rate network intrusion detection technology
• Specialized hardware for deep network packet filtering
• A high speed reconfigurable firewall based on parameterizable FPGA-based content addressable memories

Describes a project that uses

Uses Software

• Snort

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