Easy and difficult exact covering problems arising in VLSI power reduction by clock gating

DOI10.1016/J.DISOPT.2014.08.004MaRDI QIDQ2339838zbMATH OpenOpenAlexFDO

Authors Shmuel Wimer

Publication date 9 April 2015

Published in Discrete Optimization (Search for Journal in Brave)

Full work available at URL https://doi.org/10.1016/j.disopt.2014.08.004

zbMATH Keywords

clock-gatingexact coveringperfect matchingVLSI power minimization

Mathematics Subject Classification ID

Vertex subsets with special properties (dominating sets, independent sets, cliques, etc.) (05C69) Graph theory (including graph drawing) in computer science (68R10) Applications of design theory to circuits and networks (94C30)

Recommendations

• Using well-solvable minimum cost exact covering for VLSI clock energy minimization
• On optimal flip-flop grouping for VLSI power minimization
• Optimizing two-phase, level-clocked circuitry
• scientific article; zbMATH DE number 19351
• Clustering without replication in combinatorial circuits

Cites work

• Blossom V: A new implementation of a minimum cost perfect matching algorithm
• Graph theory
• On optimal flip-flop grouping for VLSI power minimization
• Paths, Trees, and Flowers
• Set Partitioning: A survey
• Using well-solvable minimum cost exact covering for VLSI clock energy minimization

Cited in

(2)

• Using well-solvable minimum cost exact covering for VLSI clock energy minimization
• On optimal flip-flop grouping for VLSI power minimization

Describes a project that uses

Uses Software

• Blossom V

This page was built for publication: Easy and difficult exact covering problems arising in VLSI power reduction by clock gating

Report a bug (only for logged in users!)Click here to report a bug for this page (MaRDI item Q2339838)