Optimizing two-phase, level-clocked circuitry

DOI10.1145/256292.256301MaRDI QIDQ4371702zbMATH OpenOpenAlexFDO

Authors Alexander T. Ishii, Charles E. Leiserson, Marios C. Papaefthymiou

Publication date 22 January 1998

Published in Journal of the ACM (Search for Journal in Brave)

Full work available at URL http://www.acm.org/pubs/contents/journals/jacm/1997-44/

zbMATH Keywords

polynomial-time algorithmstiming verificationlevel-clocked circuit

Mathematics Subject Classification ID

Computer system organization (68M99)

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Cited in

(8)

• scientific article; zbMATH DE number 2068042 (Why is no real title available?)
• Easy and difficult exact covering problems arising in VLSI power reduction by clock gating
• Understanding retiming through maximum average-delay cycles
• Invited paper Data rate optimization in synchronous circuits
• Variables bounding based retiming algorithm.
• Minimum inserted buffers for clock period minimization
• scientific article; zbMATH DE number 1555989 (Why is no real title available?)
• A new clocking algorithm based on polynomial manipulations

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