Optimizing two-phase, level-clocked circuitry

DOI10.1145/256292.256301zbMATH Open0883.68010OpenAlexW2066408410MaRDI QIDQ4371702FDOQ4371702

Authors: Alexander T. Ishii, Charles E. Leiserson, Marios C. Papaefthymiou 

Publication date: 22 January 1998

Published in: Journal of the ACM (Search for Journal in Brave)

Full work available at URL: http://www.acm.org/pubs/contents/journals/jacm/1997-44/

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zbMATH Keywords

polynomial-time algorithmstiming verificationlevel-clocked circuit

Mathematics Subject Classification ID

Computer system organization (68M99)

Cited In (8)

• Title not available (Why is that?)
• Easy and difficult exact covering problems arising in VLSI power reduction by clock gating
• Understanding retiming through maximum average-delay cycles
• Invited paper Data rate optimization in synchronous circuits
• Variables bounding based retiming algorithm.
• Minimum inserted buffers for clock period minimization
• Title not available (Why is that?)
• A new clocking algorithm based on polynomial manipulations

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