Invited paper Data rate optimization in synchronous circuits

DOI10.1080/00207218908925438zbMATH Open0701.94022OpenAlexW2131028487MaRDI QIDQ3479985FDOQ3479985

Authors: Jau-Ji Shen, Ferng-Ching Lin 

Publication date: 1989

Published in: International Journal of Electronics (Search for Journal in Brave)

Full work available at URL: https://doi.org/10.1080/00207218908925438

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zbMATH Keywords

data ratesynchronous circuitclock period

Mathematics Subject Classification ID

Cites Work

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Cited In (3)

• A new synchronizer design
• Retiming synchronous circuitry
• A predictive synchronizer for periodic clock domains

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