Improved competitive performance bounds for CIOQ switches
DOI10.1007/S00453-011-9539-9zbMATH Open1236.68021OpenAlexW2056954230WikidataQ58452149 ScholiaQ58452149MaRDI QIDQ2429338FDOQ2429338
Michael Segal, Alex Kesselman, Kirill Kogan
Publication date: 26 April 2012
Published in: Algorithmica (Search for Journal in Brave)
Full work available at URL: https://doi.org/10.1007/s00453-011-9539-9
competitive analysiscontrol policiesbuffered crossbar switchescombined input and output queued (CIOQ) architectures
Performance evaluation, queueing, and scheduling in the context of computer systems (68M20) Network design and communication in computer systems (68M10)
Cites Work
- Title not available (Why is that?)
- Title not available (Why is that?)
- Title not available (Why is that?)
- Maximizing throughput in multi-queue switches
- Packet mode and QoS algorithms for buffered crossbar switches with FIFO queuing
- Harmonic buffer management policy for shared memory switches
- On the Performance of Greedy Algorithms in Packet Buffering
- Scheduling policies for CIOQ switches
- Management of multi-queue switches in QoS networks
- The zero-one principle for switching networks
- Lower and Upper Bounds on FIFO Buffer Management in QoS Switches
- Best Effort and Priority Queuing Policies for Buffered Crossbar Switches
- Algorithms - ESA 2003
- An Experimental Study of New and Known Online Packet Buffering Algorithms
Cited In (12)
- Online scheduling FIFO policies with admission and push-out
- Effect of global FCFS and relative load distribution in two-class queues with dedicated servers
- The impact of processing order on performance: a taxonomy of semi-FIFO policies
- Buffer Management for Packets with Processing Times
- Tight Analysis of Priority Queuing for Egress Traffic
- Essential Traffic Parameters for Shared Memory Switch Performance
- Online packet scheduling for CIOQ and buffered crossbar switches
- Better bounds for online \(k\)-frame throughput maximization in network switches
- Scheduling with deadlines and buffer management with processing requirements
- A two-class discrete-time queueing model with two dedicated servers and global FCFS service discipline
- Admission control in shared memory switches
- Competitive buffer management for multi-queue switches in QoS networks using packet buffering algorithms
This page was built for publication: Improved competitive performance bounds for CIOQ switches
Report a bug (only for logged in users!)Click here to report a bug for this page (MaRDI item Q2429338)