Stride permutation networks for array processors

DOI10.1007/S11265-006-0031-8MaRDI QIDQ2477435zbMATH OpenOpenAlexFDO

Authors T. Järvinen, Perttu Salmela, Harri Sorokin, Jarmo Takala

Publication date 13 March 2008

Published in Journal of VLSI signal processing systems for signal, image and video technology (Search for Journal in Brave)

Full work available at URL https://doi.org/10.1007/s11265-006-0031-8

zbMATH Keywords

array processordata format converterfast fourier transforminterconnection networkparallel computationstride permutationviterbi decoding

Mathematics Subject Classification ID

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Cites work

• Architecture-oriented regular algorithms for discrete sine and cosine transforms
• Area-efficient architectures for the Viterbi algorithm. I. Theory
• Design of data format converters using two-dimensional register allocation
• Kronecker products and shuffle algebra
• One- and two-dimensional constant geometry fast cosine transform algorithms and architectures
• Parallel Processing with the Perfect Shuffle
• Recursive fast algorithm and the role of the tensor product
• Stride permutation networks for array processors

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(3)

• Stride permutation networks for array processors
• Permuting streaming data using RAMs
• scientific article; zbMATH DE number 139974 (Why is no real title available?)

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