Integration of unicast and multicast scheduling in input-queued packet switches
From MaRDI portal
Publication:2494765
Recommendations
- scientific article; zbMATH DE number 1900301
- Optimum Scheduling and Memory Management in Input Queued Switches With Finite Buffer Space
- Scheduling of an input-queued switch to achieve maximal throughput
- Asymptotic Performance Limits of Switches With Buffered Crossbars Supporting Multicast Traffic
- scientific article; zbMATH DE number 2090778
Cited in
(5)- scientific article; zbMATH DE number 2090778 (Why is no real title available?)
- scientific article; zbMATH DE number 2088474 (Why is no real title available?)
- Multicast support in multi-chip centralized schedulers in input queued switches
- scientific article; zbMATH DE number 1900301 (Why is no real title available?)
- Combined asynchronous/synchronous packet switching architecture: QoS guarantees for integrated parallel computing and real-time traffic
This page was built for publication: Integration of unicast and multicast scheduling in input-queued packet switches
Report a bug (only for logged in users!)Click here to report a bug for this page (MaRDI item Q2494765)