Energy efficient memory architecture for high speed decoding of block turbo-codes with the Fang-Buda algorithm

DOI10.1023/B:VLSI.0000047273.61038.18zbMath1084.94524OpenAlexW1974236943MaRDI QIDQ2574076

Liesbet van der Perre, Bruno Bougard, E. Brockmeyer, M. Rullmann, Francky V. M. Catthoor, Wim Dehaene

Publication date: 16 November 2005

Published in: Journal of VLSI Signal Processing Systems for Signal, Image, and Video Technology (Search for Journal in Brave)

Full work available at URL: https://doi.org/10.1023/b:vlsi.0000047273.61038.18

zbMATH Keywords

low powerVLSI architecturehigh throughputforward error correction (FEC) codes

Mathematics Subject Classification ID

Other types of codes (94B60) Decoding (94B35) Channel models (including quantum) in information and communication theory (94A40)

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