| Publication | Date of Publication | Type |
|---|
| Worst-case throughput analysis for parametric rate and parametric actor execution time scenario-aware dataflow graphs | 2021-06-22 | Paper |
Worst-case throughput analysis for parametric rate and parametric actor execution time scenario-aware dataflow graphs
(available as arXiv preprint) | 2021-06-22 | Paper |
Generic Multiphase Software Pipelined Partial FFT on Instruction Level Parallel Architectures
IEEE Transactions on Signal Processing | 2018-07-09 | Paper |
A systematic approach to classify design-time global scheduling techniques
ACM Computing Surveys | 2014-08-13 | Paper |
Cross-layer power management in wireless networks and consequences on system-level architecture
Signal Processing | 2009-10-29 | Paper |
The formalism underlying EASYMAP: A precompiler for refinement-based exploration of hierarchical data organizations
Science of Computer Programming | 2008-09-01 | Paper |
Multi-user motion JPEG2000 over wireless LAN: run-time performance-energy optimization with application-aware cross-layer scheduling
Journal of Zhejiang University. Science A | 2007-01-15 | Paper |
Programming Languages and Systems
Lecture Notes in Computer Science | 2006-10-20 | Paper |
Optimizing transmission and shutdown for energy-efficient real-time packet scheduling in clustered ad hoc networks
EURASIP Journal on Wireless Communications and Networking | 2006-09-12 | Paper |
Energy efficient memory architecture for high speed decoding of block turbo-codes with the Fang-Buda algorithm
Journal of VLSI signal processing systems for signal, image and video technology | 2005-11-16 | Paper |
| scientific article; zbMATH DE number 2086514 (Why is no real title available?) | 2004-08-11 | Paper |
Memory power reduction for high-speed implementation of turbo codes
Journal of VLSI signal processing systems for signal, image and video technology | 2003-08-25 | Paper |
Systematic application of data transfer and storage optimizing code transformations for power consumption and execution time reduction in ACROPOLIS: A pre-compiler for multimedia applications
Design Automation for Embedded Systems | 2003-03-25 | Paper |
| scientific article; zbMATH DE number 1863318 (Why is no real title available?) | 2003-02-04 | Paper |
| scientific article; zbMATH DE number 1746886 (Why is no real title available?) | 2002-05-29 | Paper |
A specification refinement methodology for power efficient partitioning of data-dominated algorithms within performance constraints
Journal of VLSI signal processing systems for signal, image and video technology | 2002-04-15 | Paper |
| scientific article; zbMATH DE number 1689864 (Why is no real title available?) | 2002-01-14 | Paper |
COMBINING BACKGROUND MEMORY MANAGEMENT AND REGULAR ARRAY CO-PARTITIONING, ILLUSTRATED ON A FULL MOTION ESTIMATION KERNEL
Parallel Algorithms and Applications | 2001-10-18 | Paper |
Power and speed-efficient code transformation of video compression algorithms for RISC processors
Journal of VLSI signal processing systems for signal, image and video technology | 2001-07-05 | Paper |
| scientific article; zbMATH DE number 1233793 (Why is no real title available?) | 1998-12-18 | Paper |
Memory size reduction through storage order optimization for embedded parallel multimedia applications
Parallel Computing | 1998-08-13 | Paper |
| scientific article; zbMATH DE number 978905 (Why is no real title available?) | 1997-02-17 | Paper |
| scientific article; zbMATH DE number 125144 (Why is no real title available?) | 1993-02-21 | Paper |
| scientific article; zbMATH DE number 125180 (Why is no real title available?) | 1993-02-21 | Paper |
| scientific article; zbMATH DE number 125182 (Why is no real title available?) | 1993-02-21 | Paper |
Deriving ASIC architectures for the Hough transform
Parallel Computing | 1990-01-01 | Paper |
