Parallel merging on the instruction systolic array
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Publication:2731075
DOI10.1080/00207160108805048zbMath0976.68020MaRDI QIDQ2731075
Publication date: 2001
Published in: International Journal of Computer Mathematics (Search for Journal in Brave)
Full work available at URL: https://doi.org/10.1080/00207160108805048
processor array; instruction systolic array; instruction broadcast array; soft systolic simulation system
Cites Work