Buying AES design resistance with speed and energy

DOI10.1007/978-3-662-49301-4_9zbMATH Open1405.94098OpenAlexW2396557491MaRDI QIDQ2803624FDOQ2803624

Authors: Rodrigo Portella do Canto, Roman Korkikian, David Naccache 

Publication date: 2 May 2016

Published in: The New Codebreakers (Search for Journal in Brave)

Full work available at URL: http://citeseerx.ist.psu.edu/viewdoc/summary?doi=10.1.1.732.5491

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zbMATH Keywords

AESfault attackCPAhalf size memorypower attackpower scrambling

Mathematics Subject Classification ID

Cryptography (94A60)

Cites Work

• Timing attacks on implementations of Diffie-Hellman, RSA, DSS, and other systems
• Title not available (Why is that?)
• Title not available (Why is that?)
• Fault analysis in cryptography. Foreword by Dan Boneh
• Power Analysis Attacks

Cited In (4)

• Protecting AES Software Implementations on 32-Bit Processors Against Power Analysis
• SCA-resistance for AES: how cheap can we go?
• Glitch and laser fault attacks onto a secure AES implementation on a SRAM-based FPGA
• Exploring the feasibility of low cost fault injection attacks on sub-threshold devices through an example of a 65nm AES implementation

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