Buying AES design resistance with speed and energy

DOI10.1007/978-3-662-49301-4_9MaRDI QIDQ2803624zbMATH OpenOpenAlexFDO

Authors Rodrigo Portella do Canto, Roman Korkikian, David Naccache

Publication date 2 May 2016

Published in The New Codebreakers (Search for Journal in Brave)

Full work available at URL http://citeseerx.ist.psu.edu/viewdoc/summary?doi=10.1.1.732.5491

zbMATH Keywords

AESfault attackCPAhalf size memorypower attackpower scrambling

Mathematics Subject Classification ID

Cryptography (94A60)

Recommendations

• SCA-resistance for AES: how cheap can we go?
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• An Efficient Side-Channel Protected AES Implementation with Arbitrary Protection Order
• Applied Cryptography and Network Security
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Cites work

• scientific article; zbMATH DE number 1878339 (Why is no real title available?)
• scientific article; zbMATH DE number 1418307 (Why is no real title available?)
• Fault analysis in cryptography. Foreword by Dan Boneh
• Power Analysis Attacks
• Timing attacks on implementations of Diffie-Hellman, RSA, DSS, and other systems

Cited in

(4)

• Protecting AES Software Implementations on 32-Bit Processors Against Power Analysis
• SCA-resistance for AES: how cheap can we go?
• Glitch and laser fault attacks onto a secure AES implementation on a SRAM-based FPGA
• Exploring the feasibility of low cost fault injection attacks on sub-threshold devices through an example of a 65nm AES implementation

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