Design and implementation of cryptographic modules on FPGAs

zbMATH Open1335.94082MaRDI QIDQ2804680FDOQ2804680

Authors: Mihai Togan, Adrian Floarea, Gigi Budariu 

Publication date: 4 May 2016

Recommendations

• Hardware implementation analysis of SHA-256 and SHA-512 algorithms on FPGAs
• Compact modular exponentiation accelerator for modern FPGA devices
• Implementation of the SHA-2 hash family standard using FPGAs
• scientific article; zbMATH DE number 1844641
• scientific article; zbMATH DE number 1941110

zbMATH Keywords

cryptographyparallelizationAESFPGASHA-1SHA-256

Mathematics Subject Classification ID

Cryptography (94A60)

Cited In (17)

• An EDA tool for implementation of low power and secure crypto-chips
• Title not available (Why is that?)
• Title not available (Why is that?)
• Hardware implementation analysis of SHA-256 and SHA-512 algorithms on FPGAs
• Parallel algorithms development for programmable devices with application from cryptography
• Accelerating the AES encryption function in openSSL for embedded systems
• Title not available (Why is that?)
• Implementation of the SHA-2 hash family standard using FPGAs
• Title not available (Why is that?)
• IDEA cryptographic processor in FPGA
• Compact modular exponentiation accelerator for modern FPGA devices
• Synthezising the \(F8\) cryptographic algorithm for programmable devices
• Title not available (Why is that?)
• Integrating FPGA/ASIC into cryptographic storage systems to avoid re-encryption
• Title not available (Why is that?)
• Title not available (Why is that?)
• Title not available (Why is that?)

This page was built for publication: Design and implementation of cryptographic modules on FPGAs

Report a bug (only for logged in users!)Click here to report a bug for this page (MaRDI item Q2804680)