Towards Line-Aware Realizations of Expressions for HDL-Based Synthesis of Reversible Circuits

DOI10.1007/978-3-319-20860-2_15zbMath1464.68104DBLPconf/rc/Al-WardiWD15OpenAlexW980683878WikidataQ59242251 ScholiaQ59242251MaRDI QIDQ2822514

Rolf Drechsler, Robert Wille, Zaid Al-Wardi

Publication date: 30 September 2016

Published in: Reversible Computation (Search for Journal in Brave)

Full work available at URL: https://doi.org/10.1007/978-3-319-20860-2_15

zbMATH Keywords

optimizationsynthesisreversible circuitshardware description languages

Mathematics Subject Classification ID

Mathematical problems of computer architecture (68M07) Other nonclassical models of computation (68Q09) Networks and circuits as models of computation; circuit complexity (68Q06)

Cites Work

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