| Publication | Date of Publication | Type |
|---|
| Formal Verification of Structurally Complex Multipliers | 2024-03-18 | Paper |
| Improving SAT Solving Using Monte Carlo Tree Search-Based Clause Learning | 2024-01-23 | Paper |
| Improved cost-metric for nearest neighbor mapping of quantum circuits to 2-dimensional hexagonal architecture | 2024-01-11 | Paper |
| Exploiting the benefits of clean ancilla based Toffoli gate decomposition across architectures | 2024-01-11 | Paper |
| Clustering-Guided SMT($$\mathcal {L\!R\!A}$$) Learning | 2023-03-21 | Paper |
| Advanced exact synthesis of Clifford+T circuits | 2023-02-03 | Paper |
| On the relation between BDDs and FDDs | 2022-08-16 | Paper |
| Finding Optimal Implementations of Non-native CNOT Gates Using SAT | 2021-11-03 | Paper |
| GenMul: Generating Architecturally Complex Multipliers to Challenge Formal Verification Tools | 2021-10-18 | Paper |
| Property-driven timestamps encoding for timeprints-based tracing and monitoring | 2020-05-05 | Paper |
| OKFDDs versus OBDDs and OFDDs | 2019-01-10 | Paper |
| The complexity of error metrics | 2018-10-19 | Paper |
| Multi-objective synthesis of quantum circuits using Genetic Programming | 2018-10-17 | Paper |
| Pseudo-Kronecker expressions for symmetric functions | 2018-07-09 | Paper |
| Towards VHDL-based design of reversible circuits. Work in progress report | 2018-03-16 | Paper |
| Efficient construction of QMDDs for irreversible, reversible, and quantum functions | 2018-03-16 | Paper |
| Semi-formal cycle-accurate temporal execution traces reconstruction | 2017-12-01 | Paper |
| Technology Mapping for Single Target Gate Based Circuits Using Boolean Functional Decomposition | 2016-09-30 | Paper |
| Towards Line-Aware Realizations of Expressions for HDL-Based Synthesis of Reversible Circuits | 2016-09-30 | Paper |
| Initial Ideas for Automatic Design and Verification of Control Logic in Reversible HDLs | 2016-08-10 | Paper |
| On the computational power of linearly transformed BDDs | 2016-06-16 | Paper |
| Complexity of reversible circuits and their quantum implementations | 2016-02-18 | Paper |
| Lazy-CSeq-SP: Boosting Sequentialization-Based Verification of Multi-threaded C Programs via Symbolic Pruning of Redundant Schedules | 2016-01-08 | Paper |
| Property Checking of Quantum Circuits Using Quantum Multiple-Valued Decision Diagrams | 2015-11-30 | Paper |
| Using πDDs in the Design of Reversible Circuits | 2015-11-30 | Paper |
| Ancilla-free synthesis of large reversible functions using binary decision diagrams | 2015-08-24 | Paper |
| Quantum Circuit Optimization by Hadamard Gate Reduction | 2014-09-02 | Paper |
| Mapping NCV Circuits to Optimized Clifford+T Circuits | 2014-09-02 | Paper |
| Equivalence Checking in Multi-level Quantum Systems | 2014-09-02 | Paper |
| Considering nearest neighbor constraints of quantum circuits at the reversible circuit level | 2014-06-13 | Paper |
| Upper bounds for reversible circuits based on Young subgroups | 2014-04-17 | Paper |
| On the “Q” in QMDDs: Efficient Representation of Quantum Functionality in the QMDD Data-Structure | 2013-12-17 | Paper |
| Reversible Circuit Synthesis of Symmetric Functions Using a Simple Regular Structure | 2013-12-17 | Paper |
| Exploiting Negative Control Lines in the Optimization of Reversible Circuits | 2013-12-17 | Paper |
| Reducing the Depth of Quantum Circuits Using Additional Circuit Lines | 2013-12-17 | Paper |
| https://portal.mardi4nfdi.de/entity/Q5389258 | 2012-04-26 | Paper |
| https://portal.mardi4nfdi.de/entity/Q5389328 | 2012-04-26 | Paper |
| High Quality Test Pattern Generation and Boolean Satisfiability | 2011-12-20 | Paper |
| Encoding OCL Data Types for SAT-Based Verification of UML/OCL Models | 2011-07-07 | Paper |
| Synthesis of quantum circuits for linear nearest neighbor architectures | 2011-06-16 | Paper |
| Towards a Design Flow for Reversible Logic | 2010-08-04 | Paper |
| Weighted \(A^*\) search - unifying view and application | 2009-09-14 | Paper |
| Test Pattern Generation using Boolean Proof Engines | 2009-06-05 | Paper |
| https://portal.mardi4nfdi.de/entity/Q3620427 | 2009-04-14 | Paper |
| https://portal.mardi4nfdi.de/entity/Q3528927 | 2008-10-17 | Paper |
| https://portal.mardi4nfdi.de/entity/Q3528928 | 2008-10-17 | Paper |
| https://portal.mardi4nfdi.de/entity/Q5444994 | 2008-02-27 | Paper |
| Formal Methods for Hardware Verification | 2007-05-02 | Paper |
| Correct Hardware Design and Verification Methods | 2006-10-20 | Paper |
| https://portal.mardi4nfdi.de/entity/Q4677783 | 2005-05-13 | Paper |
| https://portal.mardi4nfdi.de/entity/Q4825902 | 2004-11-05 | Paper |
| https://portal.mardi4nfdi.de/entity/Q4448597 | 2004-02-18 | Paper |
| https://portal.mardi4nfdi.de/entity/Q4946957 | 2003-11-20 | Paper |
| https://portal.mardi4nfdi.de/entity/Q4422288 | 2003-09-03 | Paper |
| https://portal.mardi4nfdi.de/entity/Q4418398 | 2003-08-10 | Paper |
| https://portal.mardi4nfdi.de/entity/Q4805283 | 2003-05-11 | Paper |
| Minimization of Word-Level Decision Diagrams | 2003-01-22 | Paper |
| Minimization of free BDDs | 2003-01-22 | Paper |
| Verifying integrity of decision diagrams | 2003-01-22 | Paper |
| https://portal.mardi4nfdi.de/entity/Q3149543 | 2002-09-26 | Paper |
| https://portal.mardi4nfdi.de/entity/Q4544352 | 2002-08-04 | Paper |
| Binary decision diagrams in theory and practice | 2002-07-25 | Paper |
| History-based dynamic BDD minimization | 2002-07-15 | Paper |
| https://portal.mardi4nfdi.de/entity/Q2746577 | 2002-02-21 | Paper |
| https://portal.mardi4nfdi.de/entity/Q2768618 | 2002-02-03 | Paper |
| Dynamic Re-Encoding During MDD Minimization | 2002-01-01 | Paper |
| https://portal.mardi4nfdi.de/entity/Q4504717 | 2000-09-14 | Paper |
| https://portal.mardi4nfdi.de/entity/Q4263885 | 2000-08-21 | Paper |
| https://portal.mardi4nfdi.de/entity/Q4215790 | 1998-10-29 | Paper |
| https://portal.mardi4nfdi.de/entity/Q4885894 | 1996-11-04 | Paper |
| https://portal.mardi4nfdi.de/entity/Q4885887 | 1996-08-22 | Paper |
| On the relation between BDDs and FDDs | 1996-03-19 | Paper |
| Fast OFDD-based minimization of fixed polarity Reed-Muller expressions | 1996-01-01 | Paper |
