| Publication | Date of Publication | Type |
|---|
| Is simulation the only alternative for effective verification of dynamic quantum circuits? | 2024-11-13 | Paper |
| Formal Verification of Structurally Complex Multipliers | 2024-03-18 | Paper |
Improving SAT Solving Using Monte Carlo Tree Search-Based Clause Learning
Advanced Boolean Techniques | 2024-01-23 | Paper |
Improved cost-metric for nearest neighbor mapping of quantum circuits to 2-dimensional hexagonal architecture
Reversible Computation | 2024-01-11 | Paper |
Exploiting the benefits of clean ancilla based Toffoli gate decomposition across architectures
Reversible Computation | 2024-01-11 | Paper |
| Clustering-Guided SMT($$\mathcal {L\!R\!A}$$) Learning | 2023-03-21 | Paper |
Advanced exact synthesis of Clifford+T circuits
Quantum Information Processing | 2023-02-03 | Paper |
| Artifacts for the IEEE Internet of Things Journal Publication: Specification-based Symbolic Execution for Stateful Network Protocol Implementations in the IoT | 2023-01-09 | Dataset |
On the relation between BDDs and FDDs (extended abstract)
LATIN '95: Theoretical Informatics | 2022-08-16 | Paper |
| Artifacts for the 2022 ATVA Paper: SISL: Concolic Testing of Structured Binary Input Formats via Partial Specification | 2022-07-06 | Dataset |
Finding Optimal Implementations of Non-native CNOT Gates Using SAT
Reversible Computation | 2021-11-03 | Paper |
GenMul: Generating Architecturally Complex Multipliers to Challenge Formal Verification Tools
Recent Findings in Boolean Techniques | 2021-10-18 | Paper |
| Artifacts for the FDL21 Paper: In-Vivo Stack Overflow Detection and Stack Size Estimation for Low-End Multithreaded Operating Systems using Virtual Prototypes | 2021-09-08 | Dataset |
| Property-driven timestamps encoding for timeprints-based tracing and monitoring | 2020-05-05 | Paper |
OKFDDs versus OBDDs and OFDDs
Automata, Languages and Programming | 2019-01-10 | Paper |
The complexity of error metrics
Information Processing Letters | 2018-10-19 | Paper |
| Multi-objective synthesis of quantum circuits using genetic programming | 2018-10-17 | Paper |
Pseudo-Kronecker expressions for symmetric functions
IEEE Transactions on Computers | 2018-07-09 | Paper |
| Towards VHDL-based design of reversible circuits. Work in progress report | 2018-03-16 | Paper |
| Efficient construction of QMDDs for irreversible, reversible, and quantum functions | 2018-03-16 | Paper |
| Semi-formal cycle-accurate temporal execution traces reconstruction | 2017-12-01 | Paper |
Technology mapping for single target gate based circuits using Boolean functional decomposition
Reversible Computation | 2016-09-30 | Paper |
Towards line-aware realizations of expressions for HDL-based synthesis of reversible circuits
Reversible Computation | 2016-09-30 | Paper |
Initial ideas for automatic design and verification of control logic in reversible HDLs (work in progress report)
Reversible Computation | 2016-08-10 | Paper |
On the computational power of linearly transformed BDDs
Information Processing Letters | 2016-06-16 | Paper |
Complexity of reversible circuits and their quantum implementations
Theoretical Computer Science | 2016-02-18 | Paper |
Lazy-CSeq-SP: Boosting Sequentialization-Based Verification of Multi-threaded C Programs via Symbolic Pruning of Redundant Schedules
Automated Technology for Verification and Analysis | 2016-01-08 | Paper |
Property checking of quantum circuits using quantum multiple-valued decision diagrams
Reversible Computation | 2015-11-30 | Paper |
Using \(\pi\)DDs in the design of reversible circuits
Reversible Computation | 2015-11-30 | Paper |
Ancilla-free synthesis of large reversible functions using binary decision diagrams
Journal of Symbolic Computation | 2015-08-24 | Paper |
Quantum circuit optimization by Hadamard gate reduction
Reversible Computation | 2014-09-02 | Paper |
Mapping NCV Circuits to Optimized Clifford+T Circuits
Reversible Computation | 2014-09-02 | Paper |
Equivalence checking in multi-level quantum systems
Reversible Computation | 2014-09-02 | Paper |
Considering nearest neighbor constraints of quantum circuits at the reversible circuit level
Quantum Information Processing | 2014-06-13 | Paper |
Upper bounds for reversible circuits based on Young subgroups
Information Processing Letters | 2014-04-17 | Paper |
Exploiting negative control lines in the optimization of reversible circuits
Reversible Computation | 2013-12-17 | Paper |
Reducing the Depth of Quantum Circuits Using Additional Circuit Lines
Reversible Computation | 2013-12-17 | Paper |
Reversible circuit synthesis of symmetric functions using a simple regular structure
Reversible Computation | 2013-12-17 | Paper |
On the ``Q in QMDDs: efficient representation of quantum functionality in the QMDD data-structure
Reversible Computation | 2013-12-17 | Paper |
| Exact synthesis of elementary quantum gate circuits | 2012-04-26 | Paper |
| scientific article; zbMATH DE number 6028105 (Why is no real title available?) | 2012-04-26 | Paper |
| High Quality Test Pattern Generation and Boolean Satisfiability | 2011-12-20 | Paper |
Encoding OCL data types for SAT-based verification of UML/OCL models
Tests and Proofs | 2011-07-07 | Paper |
Synthesis of quantum circuits for linear nearest neighbor architectures
Quantum Information Processing | 2011-06-16 | Paper |
| Towards a design flow for reversible logic | 2010-08-04 | Paper |
Weighted \(A^*\) search - unifying view and application
Artificial Intelligence | 2009-09-14 | Paper |
| Test Pattern Generation using Boolean Proof Engines | 2009-06-05 | Paper |
| Improved SAT-based reachability analysis with observability don't cares | 2009-04-14 | Paper |
| Debugging design errors by using unsatisfiable cores | 2008-10-17 | Paper |
| scientific article; zbMATH DE number 5353387 (Why is no real title available?) | 2008-10-17 | Paper |
| Robustness and usability in modern design flows | 2008-02-27 | Paper |
Formal Methods for Hardware Verification
Lecture Notes in Computer Science | 2007-05-02 | Paper |
Correct Hardware Design and Verification Methods
Lecture Notes in Computer Science | 2006-10-20 | Paper |
| scientific article; zbMATH DE number 2168228 (Why is no real title available?) | 2005-05-13 | Paper |
| scientific article; zbMATH DE number 2114151 (Why is no real title available?) | 2004-11-05 | Paper |
| scientific article; zbMATH DE number 2044679 (Why is no real title available?) | 2004-02-18 | Paper |
| scientific article; zbMATH DE number 1423225 (Why is no real title available?) | 2003-11-20 | Paper |
| scientific article; zbMATH DE number 1974128 (Why is no real title available?) | 2003-09-03 | Paper |
| scientific article; zbMATH DE number 1962006 (Why is no real title available?) | 2003-08-10 | Paper |
scientific article; zbMATH DE number 1908585 (Why is no real title available?)
Genetic Programming and Evolvable Machines | 2003-05-11 | Paper |
Verifying integrity of decision diagrams
Integration | 2003-01-22 | Paper |
Minimization of Word-Level Decision Diagrams
Integration | 2003-01-22 | Paper |
Minimization of free BDDs
Integration | 2003-01-22 | Paper |
| scientific article; zbMATH DE number 1808036 (Why is no real title available?) | 2002-09-26 | Paper |
| scientific article; zbMATH DE number 1775523 (Why is no real title available?) | 2002-08-04 | Paper |
Binary decision diagrams in theory and practice
International Journal on Software Tools for Technology Transfer. STTT | 2002-07-25 | Paper |
History-based dynamic BDD minimization
Integration | 2002-07-15 | Paper |
Equivalence checking of digital circuits in an industrial environment
it + ti. Informationstechnik und Technische Informatik | 2002-02-21 | Paper |
| scientific article; zbMATH DE number 1700026 (Why is no real title available?) | 2002-02-03 | Paper |
Dynamic Re-Encoding During MDD Minimization
Multiple-Valued Logic | 2002-01-01 | Paper |
| scientific article; zbMATH DE number 1506311 (Why is no real title available?) | 2000-09-14 | Paper |
| scientific article; zbMATH DE number 1342294 (Why is no real title available?) | 2000-08-21 | Paper |
| scientific article; zbMATH DE number 1216154 (Why is no real title available?) | 1998-10-29 | Paper |
| scientific article; zbMATH DE number 910732 (Why is no real title available?) | 1996-11-04 | Paper |
| scientific article; zbMATH DE number 910729 (Why is no real title available?) | 1996-08-22 | Paper |
On the relation between BDDs and FDDs
Information and Computation | 1996-03-19 | Paper |
Fast OFDD-based minimization of fixed polarity Reed-Muller expressions
IEEE Transactions on Computers | 1996-01-01 | Paper |
