Formal Methods for Hardware Verification

DOI10.1007/11757283zbMATH Open1182.68019OpenAlexW2475557998MaRDI QIDQ5899152FDOQ5899152

Authors: Rolf Drechsler, Goerschwin Fey 

Publication date: 2 May 2007

Published in: Lecture Notes in Computer Science (Search for Journal in Brave)

Full work available at URL: https://doi.org/10.1007/11757283

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Mathematics Subject Classification ID

Reliability, testing and fault tolerance of networks and computer systems (68M15) Fault detection; testing in circuits and networks (94C12)

Cited In (5)

• Automation of broad sanity test generation
• Why RTL ATPG?
• Synthesis of auxiliary algorithms for preliminary assessment of stuck-at faults detection tests
• Test Pattern Generation using Boolean Proof Engines
• Automatic Generation of Combinatorial Test Data

Uses Software

• CirCUs
• zChaff
• Chaff
• BerkMin
• HANNIBAL
• HITEC
• SOCRATES
• PASSAT

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