Logic Test Pattern Generation Using Linear Codes

DOI10.1109/TC.1984.1676501zbMATH Open0544.94019OpenAlexW1720470363MaRDI QIDQ3335684FDOQ3335684

Authors: Donald T. Tang, C. L. Chen 

Publication date: 1984

Published in: IEEE Transactions on Computers (Search for Journal in Brave)

Full work available at URL: https://doi.org/10.1109/tc.1984.1676501

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• Exhaustive test pattern generation using cyclic codes
• Verification Testing—A Pseudoexhaustive Test Technique
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zbMATH Keywords

integrated circuitstest pattern generationVLSI testingexhaustive test patternslinear feedback shift-registerslinear polynomial codesLogic testing

Mathematics Subject Classification ID

Linear codes (general theory) (94B05)

Cited In (12)

• Formal Methods for Hardware Verification
• Generating a PRSA with triangular symmetry
• Analysis of a PRSA generator
• Verification Testing—A Pseudoexhaustive Test Technique
• The pseudorandom sequence of arrays
• Computational Science and Its Applications – ICCSA 2004
• Efficient VLSI fault simulation
• The use of linear sums in exhaustive testing
• Exhaustive test pattern generation using cyclic codes
• \(t\)-CIS codes over \(\mathrm{GF}(p)\) and orthogonal arrays
• Recursive generation of locally complete tests
• Graph partitioning applied to the logic testing of combinational circuits

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