Graph partitioning applied to the logic testing of combinational circuits
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- A graph partitioning heuristic for the parallel pseudo-exhaustive logical test of VLSI combinational circuits
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- Partitioning circuits for improved testability
- scientific article; zbMATH DE number 975371
- On a graph partition problem with application to VLSI layout
- Partitioning methods for satisfiability testing on large formulas
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Cites work
- scientific article; zbMATH DE number 3898565 (Why is no real title available?)
- scientific article; zbMATH DE number 3972795 (Why is no real title available?)
- scientific article; zbMATH DE number 3709564 (Why is no real title available?)
- scientific article; zbMATH DE number 3783030 (Why is no real title available?)
- scientific article; zbMATH DE number 3503127 (Why is no real title available?)
- A class of combinatorial problems with polynomially solvable large scale set covering/partitioning relaxations
- Exhaustive Generation of Bit Patterns with Applications to VLSI Self-Testing
- LSI logic testing — An overview
- Logic Test Pattern Generation Using Linear Codes
- The Weighted Syndrome Sums Approach to VLSI Testing
- Verification Testing—A Pseudoexhaustive Test Technique
Cited in
(9)- A graph partitioning heuristic for the parallel pseudo-exhaustive logical test of VLSI combinational circuits
- Study on the automatic partitioning of logic schematics
- Partitioning \(P_4\)-tidy graphs into a stable set and a forest
- PO-MOESP subspace identification of directed acyclic graphs with unknown topology
- Partitioning circuits for improved testability
- Logic Test Pattern Generation Using Linear Codes
- Application of graph theory to topology generation for logic gates
- scientific article; zbMATH DE number 140133 (Why is no real title available?)
- Effects of adding a reverse edge across a stem in a directed acyclic graph
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