Exhaustive Generation of Bit Patterns with Applications to VLSI Self-Testing

DOI10.1109/TC.1983.1676202zbMATH Open0513.94031OpenAlexW2049664543MaRDI QIDQ3659697FDOQ3659697

Authors: Zeev Barzilai, Don Coppersmith, Arnold L. Rosenberg 

Publication date: 1983

Published in: IEEE Transactions on Computers (Search for Journal in Brave)

Full work available at URL: https://doi.org/10.1109/tc.1983.1676202

zbMATH Keywords

primitive polynomialslinear feedback shift registersVLSI self-testing

Mathematics Subject Classification ID

Circuits, networks (94C99)

Cited In (8)

• Partitioning circuits for improved testability
• Fault masking probabilities with single and multiple signature analysis
• Generating a PRSA with triangular symmetry
• The pseudorandom sequence of arrays
• Efficient VLSI fault simulation
• A graph partitioning heuristic for the parallel pseudo-exhaustive logical test of VLSI combinational circuits
• The use of linear sums in exhaustive testing
• Graph partitioning applied to the logic testing of combinational circuits

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