Exhaustive Generation of Bit Patterns with Applications to VLSI Self-Testing

DOI10.1109/TC.1983.1676202MaRDI QIDQ3659697zbMATH OpenOpenAlexFDO

Authors Zeev Barzilai, Don Coppersmith, Arnold L. Rosenberg

Publication date 1983

Published in IEEE Transactions on Computers (Search for Journal in Brave)

Full work available at URL https://doi.org/10.1109/tc.1983.1676202

zbMATH Keywords

primitive polynomialslinear feedback shift registersVLSI self-testing

Mathematics Subject Classification ID

Circuits, networks (94C99)

Cited in

(8)

• A graph partitioning heuristic for the parallel pseudo-exhaustive logical test of VLSI combinational circuits
• Fault masking probabilities with single and multiple signature analysis
• Partitioning circuits for improved testability
• The use of linear sums in exhaustive testing
• Efficient VLSI fault simulation
• Graph partitioning applied to the logic testing of combinational circuits
• The pseudorandom sequence of arrays
• Generating a PRSA with triangular symmetry

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