Utilization Aware Power Management in Reliable and Aggressive Chip Multi Processors

DOI10.1109/TC.2015.2439277MaRDI QIDQ2985602zbMATH OpenOpenAlexFDO

Authors Naga Durga Prasad Avirneni, Prem Kumar Ramesh, Arun K. Somani

Publication date 16 May 2017

Published in IEEE Transactions on Computers (Search for Journal in Brave)

Full work available at URL https://doi.org/10.1109/tc.2015.2439277

Mathematics Subject Classification ID

Performance evaluation, queueing, and scheduling in the context of computer systems (68M20) Mathematical problems of computer architecture (68M07)

Cited in

(3)

• State-Retentive Power Gating of Register Files in Multicore Processors Featuring Multithreaded In-Order Cores
• Analysis and elimination of noise-induced temperature error in processor thermal control
• Power Consumption Prediction and Power-Aware Packing in Consolidated Environments

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