Minimum Parallel Binary Adders with NOR (NAND) Gates

DOI10.1109/TC.1979.1675433zbMATH Open0414.94053OpenAlexW2031516162WikidataQ56269102 ScholiaQ56269102MaRDI QIDQ3050331FDOQ3050331

Saburo Muroga, Hung Lai Chi

Publication date: 1979

Published in: IEEE Transactions on Computers (Search for Journal in Brave)

Full work available at URL: https://doi.org/10.1109/tc.1979.1675433

zbMATH Keywords

logic designminimum parallel binary addersNand gatesNor gates

Mathematics Subject Classification ID

Cited In (1)

• Parallel multipliers with NOR gates based on G-minimum adders

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