Parallel multipliers with NOR gates based on G-minimum adders

DOI10.1007/BF00978712MaRDI QIDQ3676064zbMATH OpenFDO

Authors Ging-Shung Yu, Saburo Muroga

Publication date 1984

Published in International Journal of Computer & Information Sciences (Search for Journal in Brave)

Full work available at URL https://doi.org/10.1007/BF00978712

zbMATH Keywords

logic designparallel multipliersNOR gates

Mathematics Subject Classification ID

Recommendations

• Parallel Binary Adders with a Minimum Number of Connections
• Logic Networks with a Minimum Number of NOR(NAND) Gates for Parity Functions of n Variables
• Shallow circuits and concise formulae for multiple addition and multiplication
• Minimum number of adders for implementing a multiplier and its application to the design of multiplierless digital filters
• Constant integer multiplication using minimum adders

Cites work

• scientific article; zbMATH DE number 3906401 (Why is no real title available?)
• scientific article; zbMATH DE number 3743175 (Why is no real title available?)
• Arithmetic Networks and Their Minimization Using a New Line of Elementary Units
• Majority Gate Networks
• Minimum Parallel Binary Adders with NOR (NAND) Gates

Cited in

(2)

• Carry-save multiplication schemes without final addition
• Parallel Binary Adders with a Minimum Number of Connections

This page was built for publication: Parallel multipliers with NOR gates based on G-minimum adders

Report a bug (only for logged in users!)Click here to report a bug for this page (MaRDI item Q3676064)