Parallel multipliers with NOR gates based on G-minimum adders

DOI10.1007/BF00978712zbMATH Open0562.94019MaRDI QIDQ3676064FDOQ3676064

Saburo Muroga, Ging-Shung Yu

Publication date: 1984

Published in: International Journal of Computer & Information Sciences (Search for Journal in Brave)

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zbMATH Keywords

logic designparallel multipliersNOR gates

Mathematics Subject Classification ID

Cites Work

• Majority Gate Networks
• Title not available (Why is that?)
• Minimum Parallel Binary Adders with NOR (NAND) Gates
• Title not available (Why is that?)
• Arithmetic Networks and Their Minimization Using a New Line of Elementary Units

Cited In (2)

• Carry-save multiplication schemes without final addition
• Parallel Binary Adders with a Minimum Number of Connections

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