Majority Gate Networks
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(36)- Monotone circuits for monotone weighted threshold functions
- A consideration of a practical implementation for a new convergence division
- An easily testable optimal-time VLSI-multiplier
- Efficient parallel circuits and algorithms for division
- A design of fast pipelined modular multiplier based on a diminished-radix algorithm
- Shallow circuits and concise formulae for multiple addition and multiplication
- A fully parallel algorithm for residue to binary conversion
- The computation of elementary functions in radix 2^ p
- Survey on hardware implementation of random number generators on FPGA: theory and experimental analyses
- Very fast rate 2-input fuzzy processor for high energy physics
- A novel parallel prefix adder for optimized radix-2 FFT processor
- T-count optimized Wallace tree integer multiplier for quantum computing
- Integer linear programming-based bit-level optimization for high-speed FIR decimation filter architectures
- The delay of circuits whose inputs have specified arrival times
- Digital equalization for cancellation of noise-like interferences in adaptive spatial filtering
- Cost-efficient design of a quantum multiplier-accumulator unit
- An efficient design for reversible Wallace unsigned multiplier
- A quantum multiply-accumulator
- Real-time arithmetic unit
- Modular multiplication using the core function in the residue number system
- Stability of the 7-3 compressor circuit for Wallace tree. I
- Circuit level realization of low latency radix-4 Booth scheme for parallel multipliers
- Design and performance analysis of LMS algorithm based adaptive filter embedded with CFAR detector under non-homogeneous clutter scenarios
- Matching multiplications in bit-vector formulas
- Parallel multipliers with NOR gates based on G-minimum adders
- A class of systolic multiplier units for VLSI technology
- Complexity of computation in finite fields
- Verifiable stream computation and Arthur-Merlin communication
- Decomposition of Boolean function and two-realizability
- An improved parallel algorithm for integer GCD
- Depth-efficient threshold circuits for multiplication and symmetric function computation
- Cryptanalysis of algebraic verifiable delay functions
- Symbolic computer algebra for multipliers revisited - demonstrating the significance of order and phase optimization
- Root finding with threshold circuits
- Sorting short integers
- VLSI implementation of area-efficient truncated modified booth multiplier for signal processing applications
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