FPGA-based true random number generation using circuit metastability with adaptive feedback control

DOI10.1007/978-3-642-23951-9_2zbMATH Open1401.94165OpenAlexW1717406790MaRDI QIDQ3172962FDOQ3172962

Authors: Mehrdad Majzoobi, Farinaz Koushanfar, Srinivas Devadas 

Publication date: 7 October 2011

Published in: Cryptographic hardware and embedded systems -- CHES 2011. 13th international workshop, Nara, Japan, September 28--October 1, 2011. Proceedings (Search for Journal in Brave)

Full work available at URL: https://doi.org/10.1007/978-3-642-23951-9_2

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Mathematics Subject Classification ID

Random number generation in numerical analysis (65C10) Cryptography (94A60)

Cited In (4)

• Survey on hardware implementation of random number generators on FPGA: theory and experimental analyses
• Title not available (Why is that?)
• Improved entropy bounds for parity filtered self-timed ring based random number generators
• New high entropy element for FPGA based true random number generators

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