Parallel Parsing Algorithms and VLSI Implementations for Syntactic Pattern Recognition

DOI10.1109/TPAMI.1984.4767522zbMATH Open0529.68061WikidataQ52695228 ScholiaQ52695228MaRDI QIDQ3311705FDOQ3311705

Authors:

Publication date: 1984

Published in: IEEE Transactions on Pattern Analysis and Machine Intelligence (Search for Journal in Brave)

zbMATH Keywords

Earley's algorithmsyntactic pattern recognitionVLSI arrayerror-correcting recognitionparallel CFL parsingparallel CFL recognitionparsing matrix

Mathematics Subject Classification ID

Pattern recognition, speech recognition (68T10) Theory of compilers and interpreters (68N20) Theory of operating systems (68N25)

Cited In (11)

• A parallel parsing algorithm for arbitrary context-free grammars
• An NC algorithm for recognizing tree adjoining languages
• VLSI architectures for string matching and pattern matching
• Efficient reconfigurable embedded parsers
• Efficient simulations of simple models of parallel computation by time- bounded ATMs and space-bounded TMs
• Parallel \(LL\) parsing
• parallel parsing from recurrence equations
• An efficient all-parses systolic algorithm for general context-free parsing
• Systolic parsing of context-free languages
• Efficient error-correcting parsing for (attributed and stochastic) tree grammars
• Algorithm partition and parallel recognition of general context-free languages using fixed-size VLSI architecture

This page was built for publication: Parallel Parsing Algorithms and VLSI Implementations for Syntactic Pattern Recognition

Report a bug (only for logged in users!)Click here to report a bug for this page (MaRDI item Q3311705)