Functional Verification of Programmable Embedded Architectures

DOI10.1007/B137514zbMATH Open1087.68009OpenAlexW4237136126MaRDI QIDQ3377010FDOQ3377010

Authors: Prabhat K. Mishra, Nikil Dutt 

Publication date: 27 March 2006

Full work available at URL: https://doi.org/10.1007/b137514

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zbMATH Keywords

Validation of programmable architectures

Mathematics Subject Classification ID

Introductory exposition (textbooks, tutorial papers, etc.) pertaining to computer science (68-01) Mathematical problems of computer architecture (68M07)

Cited In (7)

• Metamodeling-driven IP reuse for SoC integration and microprocessor design.
• System-on-a-chip verification. Methodology and techniques
• Digital hardware/software-systems. Specification and verification.
• Post-silicon and runtime verification for modern processors
• System-level validation. High-level modeling and directed test generation techniques.
• An architectural approach to the analysis, verification and validation of software intensive embedded systems
• Abstract Interpretation of the Physical Inputs of Embedded Programs

Uses Software

• ISDL

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