Post-silicon and runtime verification for modern processors

DOI10.1007/978-1-4419-8034-2zbMATH Open1206.68003OpenAlexW604137612MaRDI QIDQ3060705FDOQ3060705

Authors: Ilya Wagner, Valeria Bertacco 

Publication date: 8 December 2010

Full work available at URL: https://doi.org/10.1007/978-1-4419-8034-2

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zbMATH Keywords

multi-core processorsmicroprocessor-based computation

Mathematics Subject Classification ID

Introductory exposition (textbooks, tutorial papers, etc.) pertaining to computer science (68-01) Analytic circuit theory (94C05) Computer system organization (68M99)

Cited In (5)

• Silicon debug of a powerPC microprocessor using model checking
• From variability tolerance to approximate computing in parallel integrated architectures and accelerators
• Functional Verification of Programmable Embedded Architectures
• On a New Mechanism of Trigger Generation for Post-Silicon Debugging
• System-level validation. High-level modeling and directed test generation techniques.

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