Spatio-Temporal Optimization of Deep Neural Networks for Reconfigurable FPGA SoCs

DOI10.1109/TC.2020.3033730MaRDI QIDQ3390133zbMATH OpenOpenAlexFDO

Authors Biruk Seyoum, Marco Pagani, Alessandro Biondi, Sara Balleri, Giorgio C. Buttazzo

Publication date 24 March 2022

Published in IEEE Transactions on Computers (Search for Journal in Brave)

Full work available at URL https://doi.org/10.1109/tc.2020.3033730

Mathematics Subject Classification ID

Computer science (68-XX)

Recommendations

• An FPGA implementation of deep spiking neural networks for low-power and fast classification
• scientific article; zbMATH DE number 1941157
• LUTNet: Learning FPGA Configurations for Highly Efficient Neural Network Inference
• Deep-learning-based FPGA fast placement algorithm

This page was built for publication: Spatio-Temporal Optimization of Deep Neural Networks for Reconfigurable FPGA SoCs

Report a bug (only for logged in users!)Click here to report a bug for this page (MaRDI item Q3390133)