Maximal strips data structure to represent free space on partially reconfigurable FPGAs
DOI10.1080/17445760902720081zbMATH Open1177.68057OpenAlexW2046283961MaRDI QIDQ3399241FDOQ3399241
Authors: Mostafa Elbidweihy, Jerry L. Trahan
Publication date: 29 September 2009
Published in: International Journal of Parallel, Emergent and Distributed Systems (Search for Journal in Brave)
Full work available at URL: https://doi.org/10.1080/17445760902720081
Recommendations
Performance evaluation, queueing, and scheduling in the context of computer systems (68M20) Data structures (68P05)
Cites Work
Cited In (3)
This page was built for publication: Maximal strips data structure to represent free space on partially reconfigurable FPGAs
Report a bug (only for logged in users!)Click here to report a bug for this page (MaRDI item Q3399241)