Byte access method for wide data bus memory based on FPGA

DOI10.3724/SP.J.1087.2008.01605MaRDI QIDQ3406934zbMATH OpenOpenAlexFDO

Authors Xiao-Xi Ren, Ke-Huan Zhang, Renfa Li

Publication date 20 February 2010

Published in Journal of Computer Applications (Search for Journal in Brave)

Full work available at URL https://doi.org/10.3724/sp.j.1087.2008.01605

zbMATH Keywords

field programmable gate array (FPGA)memory controllerbyte alignmentSDRAM

Mathematics Subject Classification ID

Computer system organization (68M99)

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(2)

• Data storage method for systems with 8 bit microprocessors or microcontrollers
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