Towards Formal Fault Tree Analysis Using Theorem Proving
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Publication:3453105
Abstract: Fault Tree Analysis (FTA) is a dependability analysis technique that has been widely used to predict reliability, availability and safety of many complex engineering systems. Traditionally, these FTA-based analyses are done using paper-and-pencil proof methods or computer simulations, which cannot ascertain absolute correctness due to their inherent limitations. As a complementary approach, we propose to use the higher-order-logic theorem prover HOL4 to conduct the FTA-based analysis of safety-critical systems where accuracy of failure analysis is a dire need. In particular, the paper presents a higher-order-logic formalization of generic Fault Tree gates, i.e., AND, OR, NAND, NOR, XOR and NOT and the formal verification of their failure probability expressions. Moreover, we have formally verified the generic probabilistic inclusion-exclusion principle, which is one of the foremost requirements for conducting the FTA-based failure analysis of any given system. For illustration purposes, we conduct the FTA-based failure analysis of a solar array that is used as the main source of power for the Dong Fang Hong-3 (DFH-3) satellite.
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Cited in
(16)- Formal fault tree analysis -- practical experiences
- FM 2005: Formal Methods
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- Failure propagation modeling and analysis via system interfaces
- Formal dependability modeling and analysis: a survey
- Formalization of RBD-based cause consequence analysis in HOL
- Formalization of reliability block diagrams in higher-order logic
- Formal Verification of Rewriting Rules for Dynamic Fault Trees
- A framework for formal probabilistic risk assessment using \textsf{HOL} theorem proving
- Formal reliability and failure analysis of Ethernet based communication networks in a smart grid substation
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- Towards the formal reliability analysis of oil and gas pipelines
- Formalization of fault trees in higher-order logic: a deep embedding approach
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