Manufacturability aware routing in nanometer VLSI

DOI10.1561/1000000015zbMATH Open1191.68128OpenAlexW4297970700MaRDI QIDQ3569375FDOQ3569375

Authors: David Z. Pan, Minsik Cho, Kun Yuan 

Publication date: 18 June 2010

Published in: Foundations and Trends® in Electronic Design Automation (Search for Journal in Brave)

Full work available at URL: https://doi.org/10.1561/1000000015

Recommendations

• Interconnect synthesis in high speed digital VLSI routing
• scientific article; zbMATH DE number 758309
• Multiscale optimization in VLSI physical design automation
• A survey on multi-net global routing for integrated circuits
• Handbook of Algorithms for Physical Design Automation

Mathematics Subject Classification ID

Computer system organization (68M99)

Cited In (3)

• Interconnect synthesis in high speed digital VLSI routing
• Optimization of manufacturing of emitter-coupled logic to decrease surface of chip
• Combining lithography and directed self assembly for the manufacturing of vias: connections to graph coloring problems, integer programming formulations, and numerical experiments

This page was built for publication: Manufacturability aware routing in nanometer VLSI

Report a bug (only for logged in users!)Click here to report a bug for this page (MaRDI item Q3569375)