Manufacturability aware routing in nanometer VLSI

DOI10.1561/1000000015MaRDI QIDQ3569375zbMATH OpenOpenAlexFDO

Authors David Z. Pan, Minsik Cho, Kun Yuan

Publication date 18 June 2010

Published in Foundations and Trends® in Electronic Design Automation (Search for Journal in Brave)

Full work available at URL https://doi.org/10.1561/1000000015

Mathematics Subject Classification ID

Computer system organization (68M99)

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Cited in

(3)

• Combining lithography and directed self assembly for the manufacturing of vias: connections to graph coloring problems, integer programming formulations, and numerical experiments
• Optimization of manufacturing of emitter-coupled logic to decrease surface of chip
• Interconnect synthesis in high speed digital VLSI routing

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