Processor and system-on-chip simulation

DOI10.1007/978-1-4419-6175-4MaRDI QIDQ3570207zbMATH OpenOpenAlexFDO

Authors

Publication date 25 June 2010

Full work available at URL https://doi.org/10.1007/978-1-4419-6175-4

zbMATH Keywords

bus simulationcachesdesign spacehigh-level architecture software simulationmulticorevirtual platforms

Mathematics Subject Classification ID

Proceedings, conferences, collections, etc. pertaining to computer science (68-06) Computer system organization (68M99)

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Cited in

(8)

• Multimedia terminal system-on-chip design and simulation
• System-on-a-chip verification. Methodology and techniques
• Applying ELAN strategies in simulating processors over simple architectures
• Multiprocessor systems on chip. Design space exploration.
• RACE: A rapid, architectural simulation and synthesis framework for embedded processors
• Performance estimation for an EDA tool-based HW/SW co-verification environment
• Simulation research on LS RISC microprocessor
• Partitioning Strategy for Embedded Multiprocessor FPGA Systems

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