A Design for Testability of Undetectable Crosspoint Faults in Programmable Logic Arrays

DOI10.1109/TC.1983.1676277zbMath0513.94004MaRDI QIDQ3659660

Nripendra N. Biswas, K. S. Ramanatha

Publication date: 1983

Published in: IEEE Transactions on Computers (Search for Journal in Brave)

zbMATH Keywords

programmable logic arrayscross-point faultscontrol input procedurecovering row setscrosspoint-irredundant PLA'ssingle fault assumptionundetectable crosspoint faults

Mathematics Subject Classification ID

Applications of graph theory to circuits and networks (94C15) Communication theory (94A05)

Related Items (2)

Easy test generation PLAs ⋮ A testable design of programmable logic arrays with universal control and minimal overhead

This page was built for publication: A Design for Testability of Undetectable Crosspoint Faults in Programmable Logic Arrays