A Design for Testability of Undetectable Crosspoint Faults in Programmable Logic Arrays

DOI10.1109/TC.1983.1676277MaRDI QIDQ3659660zbMATH OpenFDO

Authors K. S. Ramanatha, Nripendra N. Biswas

Publication date 1983

Published in IEEE Transactions on Computers (Search for Journal in Brave)

Full work available at URL https://doi.org/10.1109/TC.1983.1676277

zbMATH Keywords

control input procedurecovering row setscross-point faultscrosspoint-irredundant PLA'sprogrammable logic arrayssingle fault assumptionundetectable crosspoint faults

Mathematics Subject Classification ID

Communication theory (94A05) Applications of graph theory to circuits and networks (94C15)

Cited in

(2)

• Easy test generation PLAs
• A testable design of programmable logic arrays with universal control and minimal overhead

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