Testability Conditions for Bilateral Arrays of Combinational Cells

DOI10.1109/TC.1986.1676653zbMATH Open0575.94030MaRDI QIDQ3695201FDOQ3695201

Authors Anastasios Vergis, Ken Steiglitz 

Publication date 1986

Published in IEEE Transactions on Computers (Search for Journal in Brave)

zbMATH Keywords

fault detectionsystolic arrayquadratic growthlinear growthone-step testabilitypreset test sequences

Mathematics Subject Classification ID

Cellular automata (computational aspects) (68Q80)

Recommendations

• A testable design of iterative logic arrays
• On the testability of iterative logic arrays
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• Built-In Testing of One-Dimensional Unilateral Iterative Arrays
• Some remarks on the test complexity of iterative logic arrays (extended abstract)

Cited in

(2)

• A testable design of iterative logic arrays
• Some remarks on the test complexity of iterative logic arrays (extended abstract)

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