Testing in two-dimensional iterative logic arrays
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combinational circuitcombinational cellsmultiple cell fault-modelsingle cell fault-modeltwo-dimensional iterative logic arrays
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Cites work
- scientific article; zbMATH DE number 3298851 (Why is no real title available?)
- A Testable Design of Iterative Logic Arrays
- Multiple Fault Detection in Arrays of Combinational Cells
- Testable Sequential Cellular Arrays
- The Design of Easily Testable VLSI Array Multipliers
- Truth-Table Verification of an Iterative Logic Array
Cited in
(10)- Built-In Testing of One-Dimensional Unilateral Iterative Arrays
- A testable design of iterative logic arrays
- Some remarks on the test complexity of iterative logic arrays (extended abstract)
- Detection of multiple faults in two-dimensional ILAs
- Testability Conditions for Bilateral Arrays of Combinational Cells
- Computations over finite monoids and their test complexity
- Test generation for iterative logic arrays based on an N-cube of cell states model
- On the testability of iterative logic arrays
- Testable design of two-dimensional cellular logic arrays for detecting struck-at and bridging faults
- Sequential fault modeling and test pattern generation for CMOS iterative logic arrays
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