Testing in two-dimensional iterative logic arrays
combinational cellscombinational circuitmultiple cell fault-modelsingle cell fault-modeltwo-dimensional iterative logic arrays
The test methods of two-dimensional (2-D) iterative logic arrays (ILAs) composed of combinational cells are considered. An ILA which can be tested by a test set whose size is a constant independent of the number of cells in the ILA is referred to as a C-testable ILA. An ILA which can be tested in a number of vectors linear to the number of cells is referred to as a linear testable ILA. The fault model assumed is that faults in a cell can change a cell behavior in any arbitrary way, as long as the cell remains a combinational circuit. At the array level, two fault-models are considered: in the single cell fault-model (SCFM) only one cell can be faulty; and in the multiple cell fault-model (MCFM) any number of cells can be faulty. Previous papers have shown the testing methods of C-testable and linear testable one-dimensional ILAs under SCFM and MCFM. In this paper, we extend those methods and use the concept of divide and conquer to generate test sets for 2-D ILAs under SCFM and MCFM. The sufficient conditions and test complexities are derived. Furthermore, some practical circuits are used for example.
- A Testable Design of Iterative Logic Arrays
- scientific article; zbMATH DE number 3298851 (Why is no real title available?)
- Multiple Fault Detection in Arrays of Combinational Cells
- Testable Sequential Cellular Arrays
- The Design of Easily Testable VLSI Array Multipliers
- Truth-Table Verification of an Iterative Logic Array
- Testable design of two-dimensional cellular logic arrays for detecting struck-at and bridging faults
- Computations over finite monoids and their test complexity
- On GID-testable two-dimensional iterative arrays
- On the testability of iterative logic arrays
- Built-In Testing of One-Dimensional Unilateral Iterative Arrays
- Sequential fault modeling and test pattern generation for CMOS iterative logic arrays
- Testability Conditions for Bilateral Arrays of Combinational Cells
- A testable design of iterative logic arrays
- Testing CMOS combinational iterative logic arrays for realistic faults
- Detection of multiple faults in two-dimensional ILAs
- Some remarks on the test complexity of iterative logic arrays (extended abstract)
- Test generation for iterative logic arrays based on an N-cube of cell states model
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