Testing CMOS combinational iterative logic arrays for realistic faults

DOI10.1016/S0167-9260(96)00000-4zbMATH Open0900.68080MaRDI QIDQ4332045FDOQ4332045

Authors: Dimitris Gizopoulos, Dimitris Nikolos, Antonis Paschalis 

Publication date: 27 February 1997

Published in: Integration (Search for Journal in Brave)

Recommendations

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zbMATH Keywords

VLSI testingC-testabilityIterative logic arraysCell fault modelLinear-testabilitySequential faultsTest pattern generation

Mathematics Subject Classification ID

Logic in artificial intelligence (68T27) Computer system organization (68M99)

Cited In (14)

• A testable design of iterative logic arrays
• Maximum ease of testability of logic circuits with respect to multiple stuck-on faults
• Testing in two-dimensional iterative logic arrays
• Some remarks on the test complexity of iterative logic arrays (extended abstract)
• Detection of multiple faults in two-dimensional ILAs
• New Design for Testability Approach for Clock Fault Testing
• Testing and Diagnosing Comparison Faults of TCAMs with Asymmetric Cells
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• Test Algorithms for ECC-Based Memory Repair in Ultimate CMOS and Post-CMOS
• MODIFIED TRANSITION MATRIX AND FAULT TESTING IN SEQUENTIAL LOGIC CIRCUITS UNDER RANDOM STIMULI WITH A SPECIFIED MEASURE OF CONFIDENCE
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• On the testability of iterative logic arrays
• Testable design of two-dimensional cellular logic arrays for detecting struck-at and bridging faults
• Sequential fault modeling and test pattern generation for CMOS iterative logic arrays

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