Testing in two-dimensional iterative logic arrays

DOI10.1016/0898-1221(87)90074-5zbMATH Open0641.94038OpenAlexW1973527898MaRDI QIDQ1101079FDOQ1101079

Authors: W.-T. Cheng, J. H. Patel 

Publication date: 1987

Published in: Computers & Mathematics with Applications (Search for Journal in Brave)

Full work available at URL: https://doi.org/10.1016/0898-1221(87)90074-5

Recommendations

• On the testability of iterative logic arrays
• A testable design of iterative logic arrays
• Testing CMOS combinational iterative logic arrays for realistic faults
• Some remarks on the test complexity of iterative logic arrays (extended abstract)
• Detection of multiple faults in two-dimensional ILAs

zbMATH Keywords

combinational circuitcombinational cellsmultiple cell fault-modelsingle cell fault-modeltwo-dimensional iterative logic arrays

Mathematics Subject Classification ID

Cites Work

• Title not available (Why is that?)
• The Design of Easily Testable VLSI Array Multipliers
• A Testable Design of Iterative Logic Arrays
• Multiple Fault Detection in Arrays of Combinational Cells
• Truth-Table Verification of an Iterative Logic Array
• Testable Sequential Cellular Arrays

Cited In (9)

• Built-In Testing of One-Dimensional Unilateral Iterative Arrays
• A testable design of iterative logic arrays
• Detection of multiple faults in two-dimensional ILAs
• Testability Conditions for Bilateral Arrays of Combinational Cells
• Computations over finite monoids and their test complexity
• Test generation for iterative logic arrays based on an N-cube of cell states model
• On the testability of iterative logic arrays
• Testable design of two-dimensional cellular logic arrays for detecting struck-at and bridging faults
• Sequential fault modeling and test pattern generation for CMOS iterative logic arrays

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