scientific article; zbMATH DE number 3922544

zbMATH Open0576.94033MaRDI QIDQ3698710FDOQ3698710

Authors: Ravi Nair, Anna R. Bruss, J. Reif 

Publication date: 1985

Title of this publication is not available (Why is that?)

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zbMATH Keywords

dual-Eulerian graphCMOS combinational circuit layoutminimal complete set of pathsminimal width layoutnegative unate Boolean functionsoptimal VLSI layoutseries- parallel graph

Mathematics Subject Classification ID

Graph theory (including graph drawing) in computer science (68R10) Eulerian and Hamiltonian graphs (05C45) Applications of graph theory to circuits and networks (94C15)

Cited In (11)

• A logic-topological calculus for the construction of integrated circuits. II.
• Euler paths in series parallel graphs
• Transistor chaining in static CMOS functional cells of arbitrary planar topology
• Title not available (Why is that?)
• An algebraic technique for generating optimal CMOS circuitry in linear time
• An assignment algorithm with applications to integrated circuit layout
• Finding Double Euler Trails of Planar Graphs in Linear Time
• Linear placement algorithms and applications to VLSI design
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• Application of graph theory to topology generation for logic gates
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