Three-Dimensional Circuit Layouts

DOI10.1137/0215057zbMath0612.68063OpenAlexW1983982468MaRDI QIDQ3753506

Arnold L. Rosenberg, Frank Thompson Leighton

Publication date: 1986

Published in: SIAM Journal on Computing (Search for Journal in Brave)

Full work available at URL: https://doi.org/10.1137/0215057

zbMATH Keywords

VLSIgraph embeddingsgraph layoutsarea-volume tradeoffsmultilayer circuit realizationsone-active layer layouts

Mathematics Subject Classification ID

Analysis of algorithms and problem complexity (68Q25) Graph theory (including graph drawing) in computer science (68R10) Graph theory (05C99) Applications of graph theory to circuits and networks (94C15)

Related Items (12)

Optimal three-dimensional layouts of complete binary trees ⋮ Communication-efficient parallel algorithms for distributed random-access machines ⋮ A compact layout for the three-dimensional tree of meshes ⋮ Routing vertex disjoint Steiner-trees in a cubic grid and connections to VLSI ⋮ Optimal placement of UV-based communications relay nodes ⋮ Representations of graphs and networks (coding, layouts and embeddings) ⋮ Optimal three-dimensional layout of interconnection networks ⋮ Upward three-dimensional grid drawings of graphs ⋮ Planar acyclic computation ⋮ Complexities of layouts in three-dimensional VLSI circuits ⋮ Planar Graphs of Bounded Degree Have Bounded Queue Number ⋮ An asymptotically optimal layout for the shuffle-exchange graph

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