Semiconductor final test scheduling with Sarsa( , k) algorithm
DOI10.1016/J.EJOR.2011.05.052zbMATH Open1237.90153OpenAlexW1532749141MaRDI QIDQ421685FDOQ421685
Authors: Zhicong Zhang, Li Zheng, Forest Hou, Na Li 
Publication date: 14 May 2012
Published in: European Journal of Operational Research (Search for Journal in Brave)
Full work available at URL: https://doi.org/10.1016/j.ejor.2011.05.052
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Cites Work
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- A policy gradient method for semi-Markov decision processes with application to call admission control
- Capacity planning with reconfigurable kits in semiconductor test manufacturing
- Autonomous vehicle navigation using evolutionary reinforcement learning
- Convergence results for single-step on-policy reinforcement-learning algorithms
- Experimental analysis on Sarsa(λ) and Q(λ) with different eligibility traces strategies
- Capacity-constrained scheduling for a logic IC final test facility
- Scheduling of wafer test processes in semiconductor manufacturing
- Multi-objective optimization of water-using systems
Cited In (3)
- Semiconductor final-test scheduling under setup operator constraints
- A SIMULATED ANNEALING ALGORITHM FOR SYSTEM-ON-CHIP TEST SCHEDULING WITH, POWER AND PRECEDENCE CONSTRAINTS
- Scheduling semiconductor multihead testers using metaheuristic techniques embedded with lot-specific and configuration-specific information
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