An approach to test synthesis from higher level

DOI10.1016/S0167-9260(98)00023-6zbMATH Open0908.68073WikidataQ127279380 ScholiaQ127279380MaRDI QIDQ4225366FDOQ4225366

Authors Michiko Inoue, Hideo Fujiwara

Publication date 12 January 1999

Published in Integration (Search for Journal in Brave)

zbMATH Keywords

testabilityhigh-level synthesisnon-scan designsequential ATPG

Mathematics Subject Classification ID

Hardware implementations of nonnumerical algorithms (VLSI algorithms, etc.) (68W35) Computer system organization (68M99)

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Cited in

(6)

• High-level test synthesis: a survey
• High-level synthesis techniques for functional test pattern execution
• Functional Level Primitives in Test Generation
• Test-design through abstraction: A systematic approach based on the refinement calculus
• High level synthesis for loop-based BIST
• Synthesis for testability: Binary Decision Diagrams

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