A backtracing-oriented procedure for the analysis of combinational gate-level designs

DOI10.1016/0167-9260(94)90005-1MaRDI QIDQ4332009zbMATHOpenAlexFDO

Authors Gabriel M. Silberman, Ilan Y. Spillinger

Publication date 27 February 1997

Published in Integration (Search for Journal in Brave)

Full work available at URL https://doi.org/10.1016/0167-9260(94)90005-1

zbMATH Keywords

Circuit analysisAutomatic test pattern generationBacktracingDesign decompositionGate level design

Mathematics Subject Classification ID

Parallel algorithms in computer science (68W10) Computer system organization (68M99)

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(2)

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• A note on detecting sneak paths in transistor networks

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