A two-stage hardware scheduler combining greedy and optimal scheduling

DOI10.1016/j.jpdc.2008.07.008zbMath1243.68111OpenAlexW1982009164MaRDI QIDQ436901

Zhu Ding, Alex K. Jones, Raymond R. Hoare

Publication date: 26 July 2012

Published in: Journal of Parallel and Distributed Computing (Search for Journal in Brave)

Full work available at URL: https://doi.org/10.1016/j.jpdc.2008.07.008

zbMATH Keywords

schedulingmaximum matchingcircuit switchinghardware accelerationlarge cardinality cross bartime division multiplexing

Mathematics Subject Classification ID

Graph theory (including graph drawing) in computer science (68R10) Parallel algorithms in computer science (68W10) Performance evaluation, queueing, and scheduling in the context of computer systems (68M20)

Related Items (1)

Data-driven adaptive observer for fault diagnosis

Uses Software

• NAS Parallel Benchmarks

Cites Work

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• Matching is as easy as matrix inversion
• Distributed algorithm for approximating the maximum matching
• Matrices Associated With the Hitchcock Problem
• Efficient algorithms for finding maximum matching in graphs
• An Efficient Implementation of Edmonds' Algorithm for Maximum Matching on Graphs
• Efficient time slot assignment algorithms for TDM hierarchical and nonhierarchical switching systems
• Maximum matching in a convex bipartite graph

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