A two-stage hardware scheduler combining greedy and optimal scheduling

DOI10.1016/J.JPDC.2008.07.008MaRDI QIDQ436901zbMATH OpenOpenAlexFDO

Authors Raymond R. Hoare, Zhu Ding, Alex K. Jones

Publication date 26 July 2012

Published in Journal of Parallel and Distributed Computing (Search for Journal in Brave)

Full work available at URL https://doi.org/10.1016/j.jpdc.2008.07.008

zbMATH Keywords

schedulingmaximum matchingcircuit switchinghardware accelerationlarge cardinality cross bartime division multiplexing

Mathematics Subject Classification ID

Graph theory (including graph drawing) in computer science (68R10) Performance evaluation, queueing, and scheduling in the context of computer systems (68M20) Parallel algorithms in computer science (68W10)

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Cites work

• scientific article; zbMATH DE number 1303560 (Why is no real title available?)
• scientific article; zbMATH DE number 1955830 (Why is no real title available?)
• An Efficient Implementation of Edmonds' Algorithm for Maximum Matching on Graphs
• Distributed algorithm for approximating the maximum matching
• Efficient algorithms for finding maximum matching in graphs
• Efficient time slot assignment algorithms for TDM hierarchical and nonhierarchical switching systems
• Matching is as easy as matrix inversion
• Matrices Associated With the Hitchcock Problem
• Maximum matching in a convex bipartite graph

Cited in

(1)

• Data-driven adaptive observer for fault diagnosis

Describes a project that uses

Uses Software

• NAS Parallel Benchmarks

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