The importance of prepass code scheduling for superscalar and superpipelined processors

DOI10.1109/12.372029MaRDI QIDQ4419657zbMATH OpenOpenAlexFDO

Authors Pohua P. Chang, Daniel M. Lavery, Scott A. Mahlke, Wen-Mei W. Hwu, William Yun Chen

Publication date 15 October 2003

Published in IEEE Transactions on Computers (Search for Journal in Brave)

Full work available at URL http://hdl.handle.net/2142/74514

zbMATH Keywords

code optimizerregister allocation

Mathematics Subject Classification ID

Performance evaluation, queueing, and scheduling in the context of computer systems (68M20)

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(5)

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• Using integer linear programming for instruction scheduling and register allocation in multi-issue processors
• HIGH SPEED SYNCHRONIZATION FOR A STATICALLY SCHEDULED SUPERSCALAR PROCESSOR
• Three architectural models for compiler-controlled speculative execution
• Efficient exploitation of instruction-level parallelism for superscalar processors by the conjugate register file scheme

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