Profile-assisted instruction scheduling

DOI10.1007/BF02577873MaRDI QIDQ1329105zbMATH OpenOpenAlexFDO

Authors Scott A. Mahlke, Nancy J. Warter, Sadun Anik, Wen-Mei W. Hwu, William Yun Chen

Publication date 29 June 1994

Published in International Journal of Parallel Programming (Search for Journal in Brave)

Full work available at URL https://doi.org/10.1007/bf02577873

zbMATH Keywords

instruction schedulingprofile informationVLIW processors

Mathematics Subject Classification ID

Performance evaluation, queueing, and scheduling in the context of computer systems (68M20) Theory of compilers and interpreters (68N20)

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Cited in

(18)

• Backtracking-based instruction scheduling to fill branch delay slots
• COMPILER TECHNIQUES FOR OPTIMIZING MEMORY AND REGISTER USAGE ON THE CRAY 2
• The Performance Impact of Exploiting Branch ILP with Tree Representation of ILP Code
• Compiler-based multiple instruction retry
• The importance of prepass code scheduling for superscalar and superpipelined processors
• Three architectural models for compiler-controlled speculative execution
• Efficient exploitation of instruction-level parallelism for superscalar processors by the conjugate register file scheme
• Tree traversal scheduling: A global instruction scheduling technique for VLIW/EPIC processors
• Code positioning for VLIW architectures
• Treegion scheduling for highly parallel processors
• Value-profile guided stride prefetching for irregular code
• The impact of alias analysis on VLIW scheduling
• Instruction wake-up in wide issue superscalars
• SIP: Performance tuning through source code interdependence
• Dynamically scheduling VLIW instructions
• On the boosting of instruction scheduling by renaming
• A theory for co-scheduling hardware and software pipelines in ASIPs and embedded processors
• A software instruction prefetching method in architectures with static scheduling

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