On polynomial-time testable combinational circuits

DOI10.1109/12.324562MaRDI QIDQ4419803zbMATH OpenOpenAlexFDO

Authors Shunichi Toida, N. S. V. Rao

Publication date 1994

Published in IEEE Transactions on Computers (Search for Journal in Brave)

Full work available at URL https://doi.org/10.1109/12.324562

zbMATH Keywords

NP-completenesstest generation

Mathematics Subject Classification ID

Reliability, testing and fault tolerance of networks and computer systems (68M15) Fault detection; testing in circuits and networks (94C12)

Recommendations

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Cited in

(2)

• The Complexity of Fault Detection Problems for Combinational Logic Circuits
• On the number of minimal tests checking the block circuits of parity functions for closings

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